QUESTION:
We're currently designing a T1 to DS3 multiplexer. It is our understanding that DS3 timing is independent of the embedded T1 timing
(M13 mux allows the rate adaptation.) Given this, is there any reason why we need a PLL for retiming the DS3? Can we discard the received DS3 timing and always use a free-running oscillator for transmit DS3 timing?
ANSWER:
The short answer is... yes. The asynchronous hierarchy (DS1-DS2-DS3...) was conceived with the notion of free-running oscillators for the DS3 (and DS2) and the bit-stuffing mechanism (rate adaptation) designed to allow a wide frequency offset. However, I would suggest the following:
a) The DS2 signal was never very popular and exists, generally speaking; only within the DS3 level multiplexers and DS3 signal itself. Consequently it is possible to define the DS2 clock as "locked" to the DS3 clock. The stuffing pattern (DS2 to DS3 multiplexing) then becomes "fixed". The "C-bit parity" mode utilizes this situation to advantage. All "modern" M13 multiplexers should support C-bit parity operation.
b) The DS3 transmit clock can indeed be derived from a free-running oscillator. However, there are some standards (e.g. ITU-T G.703, ANSI T1.102, etc.) that specify what the required accuracy and stability of this oscillator must be. The DS3 bit rate must be within, generally speaking, 20 ppm.
c) I would recommend providing the option (provisionable) to operate in either the free-run or "locked" (using the received DS3 timing) mode. Whereas not technically necessary, providing the option may be required for competitive reasons (most "modern" M13 multiplexers have this option). There is a drawback to operating in the "locked" mode because it is quite easy for the craftsperson to mis-provision the multiplexers at the two ends of the DS3 link, creating a timing loop. If there was some way to detect this situation and prevent the frequency from drifting away more than 20 ppm you have a winner!
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