QUESTION:
Everything I read stresses that Composite Clock is required for DS0
interconnections. A DS3/DS1/DS0 cross-connect vendor I am dealing with
only provides the capability to externally time their equipment with a
DS1. Their equipment makes cross-connects at the DS0 level. They claim
they have been doing this for a long time on numerous networks and have
no problems. I don't understand how this can be true. What types of
problems should this synchronization limitation (DS1) cause for the DS0
circuits?
ANSWER:
Generally speaking DS3/DS1/DS0 cross-connects have only DS3 and DS1 interfaces. The DS0s are carried inside the DS1s, which may be carried within a DS3. Properly timing these interfaces requires just a suitable frequency reference (the notion of phase is not that important) for controlling the 1.544 MHz clocks and thus, implicitly, the 64 kHz timing of the DS0s. There is no DS0 interface on such a machine. That is why composite clock is not required.
The reason that composite clock is required stems from the way that 64 kbps signals (DS0s) are transported on individual cable pairs. Whenever digital (binary) data is carried over a cable pair, the transmitter constructs the digital waveform applied to the cable using, for example a "HIGH" for a "1" and a "LOW" for a "0". This results in a waveform that looks like a square wave at the transmitter. Because of the cable attenuation and capacitive roll-off, the signal gets rounded by the time it reaches the receiver. To accurately extract the data (binary "1"s and "0"s) the receiver samples the signal and compares the voltage with a suitable threshold. Greater than threshold is interpreted as a "1"; lower is interpreted as a "0". The question arises, how does the receiver know when to sample this waveform? For transport of 64 kbps signals over cable pairs in an intra-office environment, the standard way is for the BITS clock to provide a clock signal to all transmitters and receivers. This is the composite clock signal. The transmitter launches each bit as a high or low voltage at instants determined by the composite clock. Likewise, the receiver samples the received voltage signal at instants determined by the composite clock signal. That way we ensure that the receiver is sampling at the correct instant. Actually the 64 kbps (DS0 data) signal contains octets (bytes). How does the receiver know which incoming bit corresponds to the most-significant bit (MSB) of a byte. That is how does the receiver look at the bit-stream and determine the byte boundaries? This too is achieved by the composite clock which provides the octet marker via a bipolar violation in the composite clock waveform.
|
