QUESTION:
What exactly is meant by "clock recovery"? How is it implemented? When is it needed? And, what is the notion of "clocked out"?
ANSWER:
Regarding "clock recovery":
Very often the transmission of serial digital data (a bit stream) is done using a single pair of wires. Examples are DS1 (1.544 Mbps) and E1 (2.048 Mbps). Typically, a digital "1" is translated into a pulse (either with positive or negative polarity); a digital "0" is represented by the absence of a pulse. Implicit is the notion of "bit-time", the time interval allocated for the transmission of a bit. For the receiver to extract the digital data, it must establish what is the underlying bit-time. In essence, this is "clock recovery".
In other words, the receiver establishes the end-points of each bit position [the start of bit time "(n+1)" coincides with the end of bit time "n"] and can then examine the signal within each bit "window" to decide whether there was a pulse present in that window or not. As a consequence, the receiver can create a periodic "digital clock" signal that has rising edges at the bit time boundaries (or, by using suitable delaying mechanisms, in the middle of the bit time or any other well-defined point within the bit time). This then is the "recovered clock".
It helps the receiver if the signal contains many pulses since this is an active state; the absence of a pulse is passive. Receivers run into difficulty with long strings of "zeros" (absence of pulses) and thus special techniques are used (B8ZS in DS1; HDB3 in E1) to ensure that special pulse patterns are substituted for strings of zeros.
Regarding "How it is implemented":
There are many techniques available for clock recovery. In the case of DS1 or E1, the incoming signal is "sliced" by using a comparator that compares the magintude of the line signal voltage against a threshold. Considering that the DS1/E1 signal format uses "return-to-zero" pulses (ensuring that there will be only one pulse in any bit-time, of duration nominally half a bit-time), the comparator output will be a pulse in each bit-time that the line signal had a "1". A non-zero threshold is necessary to avoid false operation due to (low level) noise voltages. If the serial data was an "all-ones" signal, the comparator output would be a "digital clock" waveform with one pulse in each bit-time. The comparator output then is the "digital clock" waveform with the caveat that there are missing pulses where a pulse was absent on the line (a "zero" bit). Modern clock recovery circuits use digital phase locked loops (DPLLs) to "fill in" the missing pulses.
Regarding "when it is needed":
It is needed to extract the data from a line signal. The only case it is not needed is when the data is transmitted (usually in a non-return-to-zero format) on one cable pair and the associated clock signal (that defines the bit-time boundaries) on a separate cable pair.
Regarding the notion of "clocked out":
Every bit stream has an implicit clock signal associated with it. Logically speaking, one can imagine the actual serial data as being contained in some form of memory. The notion of "clocking out" is the use of a "digital clock" waveform to transfer this data from the memory element to the line driver for output purposes.
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