QUESTION:
If a line card receives redundant external timing for its optical transmitter from a Stratum 3E reference, can the line card use phase buildout in its own external timing selection switch? The only other requirement that seems to bear on this question is Stratum 3E Clock traceability through a network. Does Stratum 3E traceability mean that phase build out cannot be used at any clock cleaning or processing PLL until the optical data, and therefore timing, is dropped when retimed to BITS at a remote network element? This seems unlikely since, for example, wander can appear between network elements due to temperature fluctuations in the delay through optical fiber. GR-1244 stipulates that a Stratum 3E source in a network element internal timing source must not use phase buildout. From December 2000 Issue 2; R5-16 [117] Stratum 3, 4E and 4 clocks shall not perform phase build-out. On the other hand, GR-253, September 2000, Issue 3, requires; 5.4.4.3.5 Jitter and Errors During Synchronization Rearrangement Operations In general, the MTIE criteria in Section 5.4.4.3.3 could be interpreted to allow nearly instantaneous phase jumps of up to 20 ns. This is clearly undesirable from a jitter point of view. The following objective addresses this concern. It is expected that this objective will become a requirement in the future. O5-143 [928v2] The SONET outputs of an NE should meet the jitter generation requirement in Section 5.6.2.3.6 during the synchronization rearrangement activities listed in Section 5.4.4.3.3 and recovery from self-timing. O5-146 [262v2] Clock hardware protection switching should cause no errors on payload traffic. Therefore it appears that phase buildout is permissable at the line card external timing selection switch as far as GR-253 is concerned.
ANSWER:
You are generally correct that Network Elements (such as SONET/SDH ADMs) that receive multiple reference inputs need to be aware that reference switching may be necessary and that the two (or more) reference inputs, while (ideally) providing identical time-base (i.e. frequency) information, could (and probably will) have a (nominally) fixed phase offset between them. If the NE decides, for some reason, to switch between two input references, it would just appear natural, and correct, to follow just the implicit time-base but not the phase.
In the case of BITS equipment (aka SSU, SASE, etc.) the situation is somewhat different. The higher performance clocks (3E and better) are "filtering clocks". They are not "following clocks" like the lower performance clocks. Hence the "requirement" of phase build out for 3E and higher whereas "not required" for 3 and lower.
GR-253 deals with NEs whereas GR-1244 deals with clock sources.
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